Typically, chip level input/output (IO) interfaces are tested and characterized separately against interface requirements. When two chips are connected on a PCB, minimal system level testing is done using Boundary Scan testing which targets “stuck-at” faults (e.g., short circuits, open circuits). This typically meets the requirements as these interfaces are already characterized completely.
In a multichip module (MCM), multiple semiconductor dies are packaged onto a unifying substrate. The two dies have an interface between them. In MCM devices, the individual die I/Os are not characterized separately unlike chip-level I/Os. Creating test cases manually, for testing and charactering MCM interfaces can be tedious and error-prone and may even prove impossible, as tests targeting multiple fault types need to be taken into account. If these MCM IOs and interconnects are not tested and characterized completely, it can potentially cause functional failures. Hence simple boundary scan testing, which targets stuck-at faults, may not be sufficient for testing MCM interconnects.
Traditionally, MCM interconnects are tested using boundary scan testing. The two dies in an MCM have separate boundary scan test access ports associated with them. Such boundary scan testing methodology comes with all the inherent limitations of the boundary scan testing. For example, boundary scan was originally designed to test the board interconnects where the individual dies are tested and characterized and only stuck-testing is required to test the interface integrity. The interval between the update of test stimulus and capture of the response spans at least 2.5 test clock cycles. This delay makes boundary scan testing insufficient for screening of various problems such as delay defects, cross-talk, simultaneous switching noise etc. In-addition test vector generation requires boundary scan software/custom scripts.
Some at-speed testing strategies pursued for MCM testing includes functional testing, MCM built-in self test (BIST) and oscillation-based methodologies. In functional testing, test-cases are coded to target the MCM interconnect defects. In the BIST methodology, a pseudo-random pattern generator is used to generate random values on one die, and these values are captured on the other die. The values are later checked to verify the integrity of the interconnects. In the oscillation-based methodology, the traditional boundary scan cells are modified and are arranged to form a ring for creating oscillations by having odd number of cells in the ring. In these testing methodologies, targeting the faults leading to reliability issues is quite difficult. Also there is no straightforward method to isolate the failures in post silicon debug. In-addition, the MCM BIST and oscillation based test methodologies involves additional hardware and the targeted tests for traditional fault models are not possible. Also, none of the existing methods take into account clocking and process variations between the dies.